Recently, with the development of new semiconductor manufacturing processes and the extension of a memory device applications, memory devices with large capacitance have been developed. Specifically, DRAM (Dynamic Random Access Memory) has been actively developed. DRAM is effective in very large scale integration by forming one memory cell with one capacitor and one transistor.
Three dimensional capacitor structures, such as stack type capacitor cells and trench type capacitor cells, have been designed as memory cell structures for increasing packing density, instead of the prior planar type capacitor cells.
In order to obtain sufficient cell capacitance for memory cell operation by improving integration density in the 1M and 4M DRAM, a stack type capacitor construction has been widely used. However, since the size of the cell of the capacitor in 16M DRAM is no more than half the size of 4M DRAM with a conventional stack type capacitor cell construction, sufficient cell capacitance could not be obtained. Accordingly, the double-stacked storage node, the fin structure, the cylindrical cell, the BOX structure, etc., have been suggested.
FIG. 1A to FIG. 1G illustrate the process for manufacturing the STC cell (Stacked Capacitor Cell) having a BOX structure, which is disclosed in pages 141 to 144 of Ext. Abs. 21st SSDM 89, by S. Inoue, A. Nitayama, K. Hieda and F. Horiguchi.
Referring to FIG. 1A to FIG. 1G, the fabrication process of the BOX type STC cell comprises the steps of:
a) depositing SiO.sub.2, Si.sub.3 N.sub.4 and SiO.sub.2 films on a MOS transistor (word line) formed on a substrate; PA1 b) forming a contact hole in the substrate and depositing polysilicon film over the whole surface of the structure; PA1 c) depositing SiO.sub.2, polysilicon and SiO.sub.2 films in the cited order and patterning the same; PA1 d) covering the whole surface of the structure with polysilicon film and forming a side-wall by the etching back process; PA1 e) forming a window for removing SiO.sub.2 through a storage node; PA1 f) removing SiO.sub.2 to obtain a BOX structured storage node; PA1 g) depositing dielectric film on the surface of the storage node and depositing polysilicon film for a cell plate. PA1 defining an acting region by depositing a field oxide layer on a semiconductor substrate of a first conductivity type; PA1 forming a gate electrode, a source region and a drain region of a transistor which constitutes a memory cell on the active region; forming a first conductive layer on a predetermined portion of the field oxide film; and forming a first insulating layer on the gate electrode and the first conductive layer; PA1 forming a second insulating layer on the resultant structure; PA1 forming an opening in order to expose a portion of the source region and then depositing a second conductive layer on the entire surfaces of the second insulating layer and of the exposed substrate; PA1 forming a third insulating layer pattern of a saddle type by depositing a third insulating layer on the second conductive layer; PA1 depositing a third conductive layer on the resultant structure; PA1 etching the third conductive layer disposed above the source region; PA1 removing the third insulating layer pattern and forming a first electrode pattern of a capacitor; and PA1 forming a dielectric film and a fourth conductive layer in turn on the resultant structure.
Therefore, the BOX structured STC cell proposed by S. Inoue et al. can satisfy the cell capacitance required in 64M DRAM.
However, since the side-wall of the BOX structure is formed by the side-wall process in the aforementioned process for manufacturing the BOX STC structure, it has such disadvantages as described below.
Among these disadvantages are first, that the etching process is complicated because SiO.sub.2 film, polycrystalline silicon film and SiO.sub.2 film should be sequentially etched (Refer to FIG. 1C) to obtain the storage node pattern and then the etching back process (Refer to FIG. 1D) must be performed to form the side-wall. Further, SiO.sub.2 /polysilicon layers should be successively etched when forming a window (Refer to FIG. 1E).
The second disadvantage is that the regulation of the etching rate in the side-wall forming process is difficult. When the etching rate is low, pointed ends can occur after removing the SiO.sub.2 film, as shown in FIG. 1F. And when an electric field is focused on the pointed ends, it can result in the breakdown of the dielectric film and the leakage of current and can prevent the uniform coating with the dielectric film on the surface of the storage node. Also, when the etching rate is high, the side-wall becomes thin which results in the weakening of the connection between the poly-layers of the storage node.
As a result of these disadvantages, the operation efficiency and the yield of the product are lowered.